In portable electronic devices, such as mobile communication devices, reducing power consumption is one of the key requirements in the respective integrated circuit design. One of the methods for reducing the power consumption is using dual operation mode, in which the normal operation of the integrated circuit may use normal operation voltage VDD, which is high enough to drive the integrated circuit to achieve required high performance. In other operations, not so demanding to the performance, a gated-VDD may be used to provide power to the integrated circuits. Under the gated-VDD that is lower than the operation voltage VDD, less power is consumed. The gated-VDD, although causing the performance of the integrated circuit to be sacrificed, is not an issue in certain operations, such as in the power down mode or standby mode.
FIG. 1 illustrates a conventional circuit capable of providing operation voltage VDD and a gated-VDD. PMOS transistors P1 and P2 are used to control whether operation voltage VDD or the gated-VDD is supplied to main circuit 102. By supplying a low voltage to the gate of PMOS transistor P1 and a high voltage to the gate of PMOS transistor P2, operation voltage VDD is provided to main circuit 102. Conversely, by supplying a high voltage to the gate of PMOS transistor P1 and a low voltage to the gate of PMOS transistor P2, the gated-VDD, which equals voltage VDD minus the voltage drop on diode D1, is provided to main circuit 102.
The conventional circuit, however, suffers from drawbacks. FIG. 2 schematically illustrates an I-V curve of diode D1. It is noted that voltage drop Vdiode is related to the current Idiode flowing through diode D1, and a fluctuation ΔI in current Idiode causes a fluctuation ΔV in voltage drop Vdiode, and vice versa. Therefore, the gated-VDD varies when the current Idiode flowing through diode D1 varies.
In addition, the voltage-drop Vdiode and the gated-VDD are also affected by process variations and temperature variations. For example, the gated-VDD of one circuit working at a slow-slow (SS) process corner, meaning both PMOS and NMOS transistors have slow performance and low power consumption, may have a gated-VDD of about 0.707 volts. Another circuit having the same circuit design but working at a fast-slow (FS) process corner, meaning NMOS transistors are fast while PMOS transistors are slow, however, may only have a gated-VDD of about 0.579 volts. Such low voltage may cause main circuit 102 to malfunction. For example, the memories in main circuit 102 may lose data. A solution is thus needed to reduce the variation in the gated-VDD.